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V436664S24V 3.3 VOLT 64M x 64 HIGH PERFORMANCE UNBUFFERED SDRAM MODULE
PRELIMINARY
CILETIV LESO M
Features
168 Pin Unbuffered 67,108,864 x 64 bit Oganization SDRAM Modules Utilizes High Performance 32M x 8 SDRAM in TSOPII-54 Packages Fully PC Board Layout Compatible to INTEL'S Rev 1.0 Module Specification Single +3.3V ( 0.3V) Power Supply Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All Inputs, Outputs are LVTTL Compatible 8192 Refresh Cycles every 64 ms Serial Present Detect (SPD)
Description
The V436664S24V memory module is organized 67,108,864 x 64 bits in a 168 pin dual in line memory module (DIMM). The 64M x 64 unbuffered DIMM uses 16 Mosel-Vitelic 32M x 8 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.
Part Number
V436664S24VXTG-75PC
Speed Grade
-75PC, CL=2,3 (133 MHz) -75, CL=3 (133 MHz) -10PC, CL=2,3 (100 MHz)
Configuration
64M x 64
V436664S24VXTG-75
64M x 64
V436664S24VXTG-10PC
64M x 64
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Front DQM1 CS0 DU VSS A0 A2 A4 A6 A8 A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 A12 VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC
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Pin Configurations (Front Side/Back Side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Notes:
* These pins are not used in this module.
Pin Names
A0-A12 I/O1-I/O64 RAS CAS WE BA0, BA1 CKE0, CKE1 CS0-CS3 CLK0-CLK3 DQM0-DQM7 VCC VSS SCL Address Inputs Data Inputs/Outputs Row Address Strobe Column Address Strobe Read/Write Input Bank Selects Clock Enable Chip Select Clock Input Data Mask Power (+3.3 Volts) Ground Clock for Presence Detect CB0-CB7 NC DU SA0-A2 SDA Serial Data OUT for Presence Detect Serial Data IN for Presence Detect Check Bits (x72 Organization) No Connection Don't Use
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Module Part Number Information
V
MOSEL VITELIC MANUFACTURED
4
3
66
64
S
2
4
V
X
T
G - XX
SPEED 75PC = PC133 CL3,2 75 = PC133 CL3 10PC = PC133 CL3,2 LEAD FINISH G = GOLD
SDRAM 3.3V WIDTH DEPTH 168 PIN Unbuffered DIMM X8 COMPONENT REFRESH RATE 8K
COMPONENT PACKAGE, T = TSOP COMPONENT A=0.17u B=0.14u REV LEVEL LVTTL 4 BANKS
Block Diagram
CS1 CS0 DQM0 I/O1-I/O8 10 DQM1 I/O9-I/O16 10 CS3 CS2 DQM2 I/O17-I/O24 10 DQM3 I/O25-I/O32 10 E2PROM SPD (256 WORD X 8 BIT) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA VDD WP
47K
DQM CS I/O1-I/O8 D0 DQM CS I/O1-I/O8 D1
DQM CS I/O1-I/O8 D8 DQM CS I/O1-I/O8 D9
DQM4 I/O33-I/O40 10 DQM5 I/O41-I/O48 10
DQM CS I/O1-I/O8 D4 DQM CS I/O1-I/O8 D5
DQM CS I/O1-I/O8 D12 DQM CS I/O1-I/O8 D13
CS DQM I/O1-I/O8 D2 DQM I/O1-I/O8 CS D3
CS DQM I/O1-I/O8 D10 DQM I/O1-I/O8 D11 CS
DQM6 I/O49-I/O56 10 DQM7 I/O57-I/O64 10
CS DQM I/O1-I/O8 D6 CS DQM I/O1-I/O8 D7
CS DQM I/O1-I/O8 D14 CS DQM I/O1-I/O8 D15
A12-A0, BA0, BA1
D0-D15 D0-D15 C0-C31 ,C32-C42 D0-D7 D0-D15 D0-D7 VCC 10K
VSS RAS, CAS, WE CKE0
CLOCK WIRING 16M X 64 CLK0 CLK1 CLK2 CLK3 4 SDRAM +3.3pF 4 SDRAM +3.3pF 4 SDRAM +3.3pF 4 SDRAM +3.3pF
CKE1
D9-D15
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written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus)
E2PROM
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Serial Presence Detect Information
A serial presence detect storage device - - is assembled onto the module. Information about the module configuration, speed, etc. is
SPD-Table :
Byte Number Function Described
0 1 2 3 4 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access Time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM Data Width Minimum Clock Delay from Back to Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Minimum Clock Cycle Time at CAS Latency =2 Maximum Data Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time
Hex Value SPD Entry Value
128 256 SDRAM 13 10
-75PC
80 08 04 0D 0A
-75
80 08 04 0D 0A
-10PC
80 08 04 0D 09
5 6 7 8 9 10 11 12 13 14 15
2 64 0 LVTTL 7.5 ns/10.0 ns 5.4 ns/6.0 ns none Self-Refresh, 7.8s x8 n/a / x8 tccd = 1 CLK 1, 2, 4, 8 4 CL = 3, 2 CS Latency = 0 WL = 0 Non Buffered/Non Reg. Vcc tol 10% 7.5ns/10.0 ns
02 40 00 01 75 54 00 82 08 00 01
02 40 00 01 75 54 00 82 08 00 01
02 40 00 01 A0 60 00 82 08 00 01
16 17 18 19 20 21 22 23
0F 04 06 01 01 00 0E 75
0F 04 06 01 01 00 0E A0
0F 04 06 01 01 00 0E A0
24
5.4ns/6.0 ns
54
60
60
25 26
Not Supported Not Supported
00 00
00 00
00 00
27
15 ns/20 ns
0F
14
14
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SPD-Table : (Continued)
Byte Number Function Described
28 Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (Per Bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time Superset Information (May be used in Future) SPD Revision Checksum for Bytes 0 - 62 Manufacturer's JEDEC ID Code Manufacturer's JEDEC ID Code (cont.) Manufacturing Location Module Part Number (ASCII) PCB Identification Code Assembly Manufacturing Date (Year) Assembly Manufacturing Date (Week) Assembly Serial Number Reserved Intel Specification for Frequency Reserved Unused Storage Location 00 00 00 00 64 00 64 00 64 V436664S24V Mosel Vitelic Revision 2/1.2
Hex Value SPD Entry Value
14 ns/15 ns/16 ns
-75PC
0E
-75
0F
-10PC
10
29 30 31 32 33 34 35 36-61
15 ns/20 ns 42 ns/45 ns 256 MByte 1.5 ns/2.0 ns 0.8 ns/1.0 ns 1.5 ns/2.0 ns 0.8 ns/1.0 ns
0F 2A 40 15 08 15 08 00
14 2D 40 15 08 15 08 00
14 2D 40 20 10 20 10 00
62 63 64 65-71 72 73-90 91-92 93 94 95-98 99-125 126 127 128+
02 FE 40 00
02 43 40 00
12 B1 40 00
DC Characteristics
TA = 0C to 70C; VSS = 0 V; VDD, VDDQ = 3.3V 0.3V
Limit Values Symbol
VIH VIL V OH
Parameter
Input High Voltage Input Low Voltage Output High Voltage (IOUT = -2.0 mA)
Min.
2.0 -0.5 2.4
Max.
VCC +0.3 0.8 --
Unit
V V V
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Limit Values
CILETIV LESO M
Symbol
VOL II(L) IO(L)
Parameter
Output Low Voltage (IOUT = 2.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) Output leakage current (DQ is disabled, 0V < VOUT < VCC)
Min.
-- -10
Max.
0.4 10
Unit
V A A
-10
10
Capacitance
Symbol
CI1 CI2 CICL CI3 CI4 CIO CSC CSD
TA = 0C to 70C; VDD = 3.3V 0.3V, f = 1 MHz
Parameter
Input Capacitance (A0 to A11, RAS, CAS, WE) Input Capacitance (CS0-CS3) Input Capacitance (CLK0-CLK3) Input Capacitance (CKE0, CKE1) Input Capacitance (DQM0-DQM7) Input/Output Capacitance (I/O1-I/064) Input Capacitance (SCL, SA0-2) Input/Output Capacitance
Limit Values
85 30 22 50 20 20 8 18
Unit
pF pF pF pF pF pF pF pF
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Symbol
ICC1
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Absolute Maximum Ratings
Parameter
Voltage on VDD Supply Relative to V SS Voltage on Input Relative to VSS Operating Temperature Storage Temperature Power Dissipation
Max.
-1 to 4.6 -1 to 4.6 0 to +70 -55 to 125 13
Units
V V C C W
Standby and Refresh Currents1
TA = 0C to 70C, VCC = 3.3V 0.3V
Parameter
Operating Current
Test Conditions
Burst length = 4, CL = 3 tRC > = tRC(min), tCK> = tCK(min), IO = 0 mA 2 Bank Interleave Operation CKE< = VIL(max), tCK> = tCK(min) CKE< = VIL(max), tCK = Infinite CKE> = VIH(min), tCK> = tCK(min), Input changed once in 3 cycles CKE> = VIH(min), tCK = Infinite, No Input change
-75PC/75
1840
-10PC
1680
Unit
mA
Note
1,2
ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4
Precharged Standby Current in Power Down Mode Precharged Standby Current in Non-Power Down Mode
32 16 360
32 16 280
mA mA mA CS = High
40
40
mA
Active Standby Current in Power Down Mode
CKE< = VIL(max), tCK> = tCK(min) CKE< = VIL(max), tCK = Infinite
160 32 440
160 32 360
mA mA mA CS = High
Active Standby Current in Non-Pow- CKE> = VIH(min), tCK> = tCK(min), Iner Down Mode put changed one time CKE> = VIH(min), tCK = Infinite, No Input change Burst Operating Current Burst length = Full Page, tRC = Infinite, CL = 3, tCK> = tCK(min), IO = 0 mA 2 Banks Activated tRC >= tRC (min) CKE = <0,2 V
200
200
mA
1200
960
mA
1, 2
ICC5 ICC6
Auto Refresh Current Self Refresh Current
3840 48
3520 48
mA mA
1,2
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AC Characteristics 3,4
TA = 0 to 70C; VSS = 0V; VCC = 3.3V 0.3V, tT = 1 ns
Limit Values -75PC # Symbol Parameter Clock and Clock Enable
1 tCK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 System frequency CAS Latency = 3 CAS Latency = 2 Clock Access Time CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Input Setup time Input Hold Time CKE Setup Time (Power down mode) CKE Setup Time (Self Refresh Exit) Transition time (rise and fall) 7.5 7.5 - - - - 2.5 2.5 1.5 0.8 2.5 8 0.3 133 133 5.4 5.4 - - - - - - 1.2 7.5 10 - - - - 2.5 2.5 1.5 0.8 2 8 1 133 100 5.4 6 - - - - - - - 10 10 - - - - 3 3 2 1 2 8 1 100 100 6 6 - - - - - - - ns ns MHz MHz 4,5 ns ns ns ns ns ns ns ns ns 6 6 7 7 8 9
-75 Min. Max.
-10PC Min. Max. Unit Note
Min.
Max.
2
fCK
3
tAC
4 5 6 7 8 9 10
tCH tCL tCS tCH tCKSP tCKSR tT
Common Parameters
11 12 13 14 15 16 tRCD tRC tRAS tRP tRRD tCCD RAS to CAS delay Cycle Time Active Command Period Precharge Time Bank to Bank Delay Time CAS to CAS delay time (same bank) 15 60 42 20 14 1 - - - - - - 20 70 45 20 15 1 - 120k - - - - 20 70 45 20 20 1 - 120k - - - - ns ns ns ns ns CLK
Refresh Cycle
17 18 tSREX tREF Self Refresh Exit Time Refresh Period (8192 cycles) 10 64 - - 10 64 - - 10 64 - - ns ms 9 8
Read Cycle
19 20 21 22 tOH tLZ tHZ tDQZ Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency 2.7 1 3 2 - - 7.5 - 3 0 3 2 - - 7.5 - 3 0 3 2 - - 8 - ns ns ns CLK 10 4
Write Cycle
23 24 25 tDPL tDAL tDQW Data input to Precharge (write recovery) Data In to Active/refresh DQM Write Mask Latency 2 5 0 - - - 2 5 0 - - - 1 5 0 - - - CLK CLK CLK 11
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Notes:
1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ's) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V.
tCH 2.4V CLOCK 0.4V
+ 1.4 V 50 Ohm Z=50 Ohm I/O 50 pF
tCL
tSETUP tHOLD
tT
INPUT
1.4V
tAC tLZ tOH
tAC
I/O 50 pF
1.4V
OUTPUT
Measurement conditions for tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. 11. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. tDAL is equivalent to tDPL + tRP.
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17.80
1
3.0
10
11
40
41
84
42.18 63.68 A B
35.00
4.0
3.125
3.125
2.50
4.45
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Package Diagram
L-DIM-168-30 SDRAM DIMM Module Package
All measurements in mm 133.37
127.35
(4.0 max)
1.27 0.100
85
94
95
124
125
168
D
6.35
6.35
1.27
1.0 0.05
0.2 0.15
2.0 Detail A 2.26 3.175 Detail B
2.0 Detail C
RADIUS 1.27 + 0.10
Tolerances: (0.13) unless otherwise specified.
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Label Information
Module Density
MOSEL VITELIC
Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) DIMM manufacture date code
V436664S24VXXX-XX 512MB CLX PC133U-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan
CAS Latency 2=CL2 3=CL3
PC133 U -XXX
UNBUFFERED DIMM CL= 3 or 2 (CLK) tRCD= 3 or 2 (CLK) tRP= 3 or 2 (CLK)
54 2
A
Gerber file Intel PC100 x8 Based JEDEC SPD Revision 2
tAC = 5.4 ns
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WORLDWIDE OFFICES
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888
SINGAPORE
10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013
UK & IRELAND
SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516
JAPAN
ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402
GERMANY (CONTINENTAL EUROPE & ISRAEL)
BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
U.S. SALES OFFICES
WEST
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
CENTRAL / EAST
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029
(c) Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
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